![]() ![]() No one is thinking of 5G carrier frequencies there, but when you get up into the high-20, low-30GHz carrier bands, some of the issues you mentioned do start to come to the forefront. For example, we’ve done auto radar projects up to 77GHz. Slessor: Millimeter wave means different things to different people. SE: With RF, what’s happening with millimeter wave? What are you testing for, because signals don’t carry very far and they are easily interrupted by moving object or even weather. But for other applications, whether it be RF, apps processors or microprocessors, there’s still a tremendous amount of iteration early in design cycles. AI is one example where we’re seeing a lot of iteration, and that’s true of any place where you’re on a rapid innovation curve. That has a significant impact on the probe card and various test interfaces. For most chips, we see multiple design spins early in their lifecycle to change some aspect of either the architecture or the silicon itself. It’s happening across much of the high end of the industry. Slessor: Yes, and that’s true not just for AI. SE: Is it more iterative than it has been in the past, almost like what an IDM can do? And everybody has to work together and communicate well for these things to work. You have three customers for a single design. There are a lot of engagements where you don’t have one customer. And a lot of the test program development does go into some of the spaces of algorithm development and then how the end system is going to be deployed. There is the fabless design house, the foundry, and depending on where the test is being done, there can be a testing house, too. It’s usually multiple entities at different geographic locations that you are working with at the same time. Slessor: For the test part of the business, with any given engagement you got a very interesting customer set. SE: But now, instead of just dealing with the chipmakers, you’re dealing with the companies making the chips, the systems those chips are in, and the people who are designing everything and writing the algorithms, right? There are technical challenges, but it’s a really interesting field to be in because you’re working with some of the leading customers in the world to push this forward. FormFactor made some really big investments in MEMS probe technology, which is really the only cost-effective way to get to the kind of densities and performance levels that people need to test these kinds of chips. When you think about the density and the sheer power you need to get into the chip, and then the number of interfaces it has to the outside world - these are very complicated interfaces, and therefore very complicated tests and test tooling. Slessor: Yes, these are some very, very large die. SE: These are reticle size plus stitching to make them even larger, right? We’re actually shipping probe cards with that number of probes to test some of these AI engines, as well. State-of-the-art memory probe cards a few years ago had maybe 50,000 or 60,000 probes per card. But that whole test interface for logic chips is now approaching the numbers and scale that we saw in memory only a few years ago. To get all of the power in, there are some thermal control issues associated with test. For a probe card manufacturer, that drives a very large number of probes. We’ve seen some projects that are really mind boggling in terms of die size and transistor count. The massive parallelism of these devices is driving people to use the most advanced silicon nodes, especially for the logic part of it. Slessor: A lot of the AI stuff that we’ve been involved with is definitely at the advanced nodes. SE: How does test change with AI chips, where you’ve got massive numbers of accelerators and processors developed at 7 and 5nm? Mike Slessor, president and CEO of FormFactor, sat down with Semiconductor Engineering to discuss testing of AI and 5G chips, and why getting power into a chip for testing is becoming more difficult at each new node. ![]()
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